Research Intern — May 2022 – Aug 2022

1. Optimized scheduling of GP-GPU kernels to accelerate graph-based applications, enhancing performance and efficiency.
2. Developed and implemented the CPD-ALS framework for efficient tensor decomposition, improving computational throughput.
3. Conducted in-depth analysis to identify performance bottlenecks in GPU execution for graph applications.
4. Discovered optimization strategies for matrix multiplications involving tall and wide matrices, significantly boosting overall performance.

Junior Research Fellow — Jan 2019 – Aug 2021

1. Conducted design space exploration for NB-LDPC codes on FPGAs.
2. Developed accelerators for sparse matrix multiplication.
3. Appointed as a Visiting Research Fellow at Instituto de Telecomunicações, University of Coimbra (Mar 2021 – Jun 2021).