CV

Research Intern

Advanced Micro Devices (AMD)

Optimized the scheduling of GP-GPU kernels to accelerate graph-based applications, improving performance and efficiency.

• Worked on GPU workload scheduling optimizations for graph-based applications.
• Enhanced compute efficiency and resource utilization for AMD research workloads.

Junior Research Fellow

Centre for Heterogeneous and Intelligent Processing Systems (CHIPS)

Conducted research on FPGA-based acceleration for communication and ML workloads.

• Performed design-space exploration for NB-LDPC codes on FPGAs (SIPS ’20, IEEE Design & Test ’22).
• Developed hardware accelerators for sparse matrix multiplication (VLSID ’22).

M.S. + Ph.D.

The Ohio State University

Computer Engineering

• Computer Architecture
• Embedded Systems
• Parallel and Distributed Systems
• Operating Systems
• High-Performance Computing
• Reinforcement Learning and Machine Learning
• FPGA/SoC Design and Performance Modeling

Outstanding Paper Award, EMSOFT 2025

ACM/IEEE Embedded Systems Week

Recognized for the paper 'FC-GPU: Feedback Control GPU Scheduling for Real-time Embedded Systems'.

Best Paper Award, VLSID 2022

International Conference on VLSI Design and Embedded Systems

Received the A.K. Choudhary Best Paper Award for FPGA accelerator design for sparse matrix multiplication.

EMSOFT Travel Grant Award

Embedded Systems Week

Awarded travel support for presenting research at EMSOFT 2025.

BurnLin Travel Grant Award

The Ohio State University

Awarded three consecutive years (2023–2025) for research excellence in embedded and parallel systems.

Amrita Scholarship

Amrita Vishwa Vidyapeetham

Merit-based undergraduate scholarship recognizing academic excellence.

FC-GPU: Feedback Control GPU Scheduling for Real-time Embedded Systems

EMSOFT 2025

Proposed FC-GPU, a feedback-control framework for real-time GPU scheduling that reduces deadline misses by 2% using MIMO-based control.

Power Capping of GPU Servers for Machine Learning Inference Optimization

ICPP 2025

Proposed CapGPU, a coordinated CPU–GPU power-capping framework that improves inference throughput by up to 20% under latency constraints.

Exploiting ML Task Correlation in the Minimization of Capital Expense for GPU Data Centers

IEEE IPCCC 2025

Introduced CorrGPU, a correlation-aware scheduling algorithm that reduces CapEx by 20.88% in large-scale ML workloads.

Latency-Guaranteed Co-Location of Inference and Training for Reducing Data Center Expenses

IEEE ICDCS 2024

Developed GPUColo, a co-location framework that enables training and inference sharing on GPUs, saving up to 74.9% of GPU resources.

FC-GPU: Feedback-Control GPU Scheduling

Developed FC-GPU, the first feedback-control GPU scheduling framework for real-time systems using a MIMO controller to dynamically adapt task rates, reducing deadline misses by 2%.

• Best Paper Candidate, EMSOFT 2025
• Reduced deadline misses by 2% on RTX 3090 and MI100.

CapLLM: Power-Capping for LLM Data Centers

Designed CapLLM, a power-capping framework for LLM-serving data centers that minimizes performance violations while improving energy efficiency.

• Dynamic GPU power management
• Improved SLA compliance

CorrGPU: Correlation-Aware GPU Scheduling

Proposed CorrGPU, a scheduling algorithm that consolidates correlated workloads to reduce contention and lower CapEx by 20.88%.

• Correlation-aware scheduling
• Reduced CapEx by 20.88%

CapGPU: Coordinated CPU–GPU Power Capping

Implemented CapGPU, a coordinated CPU–GPU power-capping strategy improving inference throughput by 8–20% while maintaining latency SLOs.

• 8–20% throughput improvement
• Maintained SLO compliance

GPUColo: GPU Co-Location Framework

Built GPUColo, a co-location framework that enables training and inference workloads to share GPUs, saving up to 74.9% of GPUs with strict SLO compliance.

• 74.9% GPU savings
• Reduced CapEx with SLO guarantees